Technical Field
Disclosed embodiments are related to the field of integrated circuits, and more particularly to supplying power to circuitry in integrated circuits.
Description of the Related Art
As the number of transistors included on an integrated circuit “chip” continues to increase, power management in the integrated circuits continues to increase in importance. Power management can be critical to integrated circuits that are included in mobile devices such as personal digital assistants (PDAs), cell phones, smart phones, laptop computers, net top computers, etc. These mobile devices often rely on battery power, and reducing power consumption in the integrated circuits can increase the life of the battery. Additionally, reducing power consumption can reduce the heat generated by the integrated circuit, which can reduce cooling requirements in the device that includes the integrated circuit (whether or not it is relying on battery power).
Clock gating is often used to reduce dynamic power consumption in an integrated circuit, disabling the clock to idle circuitry and thus preventing switching in the idle circuitry. While clock gating is effective at reducing the dynamic power consumption, the circuitry is still powered on. Leakage currents in the idle transistors lead to static power consumption. The faster transistors (those that react to input signal changes, e.g. on the gate terminals) also tend to have the higher leakage currents, which often results in high total leakage currents in the integrated circuit, especially in high performance devices.
To counteract the effects of leakage current, some integrated circuits have implemented power gating. With power gating, the power to ground path of the idle circuitry is interrupted, reducing the leakage current to near zero. There can still be a small amount of leakage current through the switches used to interrupt the power, but it is substantially less than the leakage of the idle circuitry as a whole.
Power gating presents challenges to the integrated circuit design. As blocks are powered up and powered down, the change in current flow to the blocks can create noise on the power supply connections. The noise can affect the operation of the integrated circuit, including causing erroneous operation. Additionally, the rate of change in the current flow (di/dt) varies with process variations in the semiconductor fabrication process, and can also vary with the magnitude of the supply voltage supplied to the integrated circuit and with the operating temperature of the integrated circuit. When these factors slow the rate of change of the current, the delay to enable a power gated block increases. Accordingly, balancing the delay to enable the power gated blocks and the power supply noise is challenging.
A possible solution to balancing the delay and noise is described in U.S. Pat. No. 8,362,805 (“the '805 patent”). The '805 patent describes connecting a serial chain of flops to the enable. The output of each flop in the chain is connected to a set of power switches. Accordingly, the switches are serialized to control the ramp rate to an acceptable level. As also described in the '805 patent, the delay may also be fixed based on the clock frequency of the clock to the flops. Initial power up of an integrated circuit employing an approach described in the '805 patent may include ensuring that control for the flops is ready prior to powering up the power-gated blocks. Another possible solution is presented in U.S. Pat. No. 8,421,499 (“the '499 patent”). The '499 patent describes connecting sets of power switches with enable control circuits. Each enable control circuit may also be connected to the global block enable. If the power, voltage, and temperature (PVT) conditions indicate a slow ramp rate, the enable control circuits may select the global enable such that the power switches power up in parallel. If the PVT conditions indicate a fast ramp rate, the enable control circuits may select the power switch enable propagated from the previous set of power switches, connecting the sets of power switches in series. The '499 patent describes that the integrated circuit may include information about the manufacturing process at the time of fabrication, along with voltage magnitude information and temperature measurements. The sets of power switches may then be designed such that the fastest PVT conditions will not violate di/dt limits of the integrated circuit and such that parallel connection of the sets does not violate di/dt limits in slower PVT conditions.